1. Field of the Invention
The present invention relates to a signal processing integrated circuit device which performs a predetermined processing on an input signal such as a PCM signal and more particularly to a signal processing integrated circuit device which performs a predetermined processing on a modulated input signal.
2. Description of the Background Art
FIG. 1 is a block diagram of a conventional signal processing integrated circuit device. A test is conducted on the signal processing integrated circuit device in a manner described hereinafter. A test signal is inputted from a test signal generator 200 through an input pad 1 to an input part 3 of a signal processing circuit 2. A synchronizer (not shown) synchronizes the test signal generator 200 with the signal processing circuit 2. The signal processing circuit 2 processes the input signal and outputs a signal through an output part 4 and an output pad 5. The output signal is measured, thereby the signal processing integrated circuit device being tested.
Because of high efficiency of the test, the test signal generator 200 is required to be previously programmed such that it generates a test signal in accordance with the signal processing integrated circuit device to be tested. Particularly when the test is conducted on a signal processing integrated circuit device which processes a modulated signal, e.g., a PCM decoder for satellite broadcasting service or a PCM decoder for a compact disc, the test signal generated in the test signal generator 200 must be a modulated signal.
The conventional signal processing integrated circuit device is structured as mentioned above. The modulated signal must be inputted to the signal processing integrated circuit device to be tested for processing the modulated signal. For example, an audio signal processing integrated circuit device for use in a satellite broadcasting service receiver employs digitized audio data and audio signal demodulation information necessary for demodulating the audio data to an analog signal. For accurate reproduction of a data clock on the receiver side (corresponding to the signal processing circuit 2 of FIG. 6), a signal obtained by scrambling both of the data by means of a PN (pseudo noise) signal is used as an input signal. Thus, when the test is conducted on the audio signal processing integrated circuit device for use in the satellite broadcasting service receiver, it is necessary to produce the audio data and the audio signal demodulation information, to scramble both of the data by the PN signal, and to use the scrambled signal as an input signal.
In the test of the signal processing integrated circuit device for processing the modulated signal, it is required to produce signals capable of testing all various characteristics of the signal processing integrated circuit device and to perform a predetermined modulation on the signals. There arises a problem that complicated operations are required.
Another problem is that it is difficult to decide whether or not the generated test signal is normal because the test signal has been modulated. When a signal modulated by a pseudo-random number signal is used as in the satellite broadcasting receiver, the test signal also must be such a modulated signal. Still another problem is that a small number of repetitive data included in the signal causes a low compression rate of the test signal.
In order to solve the problems, there may be provided a modulator for modulating the test signal from the test signal generator 200 to generate a modulated signal in accordance with the signal processing circuit 2, between the test signal generator 200 and the signal processing circuit 2. This structure facilitates the operations of producing the test signal and improves the compression rate of the test signal because of the increase in the repetitive data included in the signal. This structure, however, causes another problem that two other equipments for synchronization are required because the modulator must be synchronized with both the test signal generator 200 and the signal processing circuit 2, respectively.